In most practical applications, it is necessary to provide protection structures to a semiconductor device so as to prevent the device from being damaged by a high voltage and/or a high current induced by electro-static discharge (“ESD”). Generally, for a semiconductor device, such as a metal oxide semiconductor field effect transistor (“MOSFET”), a junction field effect transistor (“JFET”), a double diffused metal-oxide semiconductor transistor (“DMOS”) etc., an ESD protection module is coupled between a gate and a source of the semiconductor device to protect a gate oxide of such a device from being damaged by ESD. The ESD protection module is configured to provide a conduction path between the source and the gate of the device once a gate to source voltage of the device caused by ESD exceeds an ESD threshold voltage, so that a large extra energy due to ESD can be discharged promptly through the conduction path. The ESD protection module is usually desired to be integrated into the semiconductor device that it is intended to protect for reducing the size and manufacturing cost of the semiconductor device.
FIG. 1 illustrates a top plan view of an ESD protection structure 50. The ESD protection structure 50 may usually be formed by doping a polysilicon layer 51 with P type and N type dopants so as to form a plurality of alternately arranged P type doped regions 511 and N type doped regions 512 in the polysilicon layer 51. The ESD protection structure 50 therefore comprises a group of PN diodes, since every two adjacent P type doped region 511 and N type doped region 512 form a PN junction. In practical application, to name an example, the ESD protection structure 50 (i.e. the group of PN diodes) can be coupled between a source metal/electrode and a gate metal/electrode of a semiconductor transistor (e.g. MOSFET, JFET, DMOS etc.) to protect a gate oxide of a gate region of the transistor from being damaged by a large extra energy due to ESD.
The shape of the ESD protection structure 50 (including the ESD polysilicon layer 51 and the P type doped region 511 and N type doped region 512) generally can have a large influence to the protection performance of the ESD protection structure 50. Still referring to FIG. 1, the ESD protection structure 50 is typically formed in round rectangle shape. However, since each corner 501 of the round rectangle shape has a larger curvature than each side 502 of the round rectangle shape, when the ESD protection structure 50 is coupled to suffer a high voltage and/or a high current induced by ESD in practical application, electric field distribution in the ESD protection structure 50 is non-uniform. The electric field is more intensive in portions having relatively larger curvature (e.g. at each corner 501) than in portions having relatively smaller curvature (e.g. at each side 502) in the ESD protection structure 50. Therefore, the portions having relatively larger curvature are more vulnerable and easier to breakdown, which limits the high-voltage withstanding capacity of the ESD protection structure 50.
Another considerable factor that determines the protection performance of the ESD protection structure 50 is the area of PN junction formed by each group of adjacent P type doped region 511 and N type doped region 512. Providing the thickness of the ESD protection structure 50 (i.e. the thickness of the polysilicon layer 51 or the thickness of the plurality of P type doped regions 511 and N type doped regions 512) is defined, the PN junction area of each group of adjacent P type doped region 511 and N type doped region 512 is determined by the perimeter of the contacting contour of each group of adjacent P type doped region 511 and N type doped region 512. For instance, in FIG. 1, the perimeter of the round rectangle shaped contour of the ESD protection structure 50 determines the PN junction area of each group of adjacent P type doped region 511 and N type doped region 512. Increasing the perimeter of the contour shape of ESD protection structure 50 can increase the PN junction area of each group of adjacent P type doped region 511 and N type doped region 512, which advantageously helps to reduce the resistance of each PN diode. In consequence, the reduction in resistance of each PN diode enhances the current conduction capacity and current distribution uniformity of the ESD protection structure 50, and thus the ESD protection structure 50 can provide better ESD protection to the semiconductor device 10.